1. Field of Disclosure
The present disclosure generally relates to clock distribution within a synchronous sequential logic circuit and specifically to using magnetic coupling to distribute a reference clocking signal from a common point to various locations within the synchronous sequential logic circuit.
2. Related Art
An electronic circuit is composed of one or more electronic components, such as resistors, transistors, capacitors, inductors, and/or diodes to provide some examples, which are connected together by conductive wires or traces. The electronic circuit can be an analog electronic circuit in which electric signals therein can vary continuously with time, a digital electronic circuit in which electric signals therein can be formed of discrete values, and/or any combination of the analog and the digital electronic circuits, often referred to as a mixed-signal or a hybrid circuit. The digital electronic circuit is often constructed from logic gates which can be used to create a combinational logic circuit. One or more combinational logic circuits can be combined with various memory elements, such as a flip-flop to provide an example, which then can be combined with other combinations of combinational logic circuits and memory elements to form a sequential logic circuit that is designed to perform a sequence of operations. The sequential logic circuit can be categorized as being either a synchronous sequential logic circuit which changes state when one or more clock signals change state or an asynchronous sequential logic circuit which changes state regardless of the one or more clock signals.
The one or more clock signals are distributed within the synchronous sequential logic circuit using a clock distribution network, also referred to a clock tree in some situations. The clock distribution network distributes the one or more clock signals from a common point to various locations within the synchronous sequential logic circuit. Often times, data within the synchronous sequential logic circuit is provided with a temporal reference by the one or more clock signals; therefore, the one or more clock signals should be particularly clean and sharp as they are being distributed by the clock distribution network. Additionally, the one or more clock signals are particularly affected by technology scaling within the synchronous sequential logic circuit. For example, long global interconnections within the clock distribution network become much more highly resistive as their dimensions are decreased. Further, delay in of the one or more clock signals attributed to the clock distribution network can severely limit maximum performance of the synchronous sequential logic circuit as well as create race conditions in the synchronous sequential logic circuit.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.